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publication# 08811 rev. g amendment /0 issue date: june 1993 2-349 PALCE29MA16h-25 24-pin ee cmos programmable array logic final com'l: h-25 distinctive characteristics n high-performance semicustom logic replacement; electrically erasable (ee) technology allows reprogrammability n 16 bidirectional user-programmable i/o logic macrocells for combinatorial/registered/ latched operation n output enable controlled by a pin or product terms n varied product term distribution for increased design flexibility n programmable clock selection with common pin clock/latch enable ( le ) or individual product term clock/ le with low/high clock/ le polarity n register/latch preload permits full logic verification n high speed (t pd = 25 ns, f max = 33 mhz and f max internal = 50 mhz) n full-function ac and dc testing at the factory for high programming and functional yields and high reliability n 24-pin 300 mil skinnydip and 28-pin plastic leaded chip carrier packages n extensive third-party software and programmer support through fusionpld partners general description the PALCE29MA16 is a high-speed, ee cmos pro- grammable array logic (pal) device designed for gen- eral logic replacement in ttl or cmos digital systems. it offers high speed, low power consumption, high programming yield, fast programming, and excellent reliability. pal devices combine the flexibility of custom logic with the off-the-shelf availability of standard products, providing major advantages over other block diagram 08811g-1 v i/o logic macrocell v i/of v i/o v i/o v i/o v i/o v v i/of v i/oe v v i/o v i/o v i/o v i/o v i/of v i/of programmable and array 58x178 i -i i/of clk/le 4 0 3 0 1 i/of 0 12 323 4 i/of 5 4 5 6 7 6 i/of 7 4 4 4 4 8 4 12 4 12 4 8 4 4 4 4 4 4 4 8 4 12 4 12 4 8 4 4 4 4 4 4 4 i/o logic macrocell i/o logic macrocell i/o logic macrocell i/o logic macrocell i/o logic macrocell i/o logic macrocell i/o logic macrocell i/o logic macrocell i/o logic macrocell i/o logic macrocell i/o logic macrocell i/o logic macrocell i/o logic macrocell i/o logic macrocell i/o logic macrocell
amd 2-350 PALCE29MA16h-25 general description (continued) semicustom solutions such as gate arrays and standard cells, including reduced development time and low up- front development cost. the PALCE29MA16 uses the familiar sum-of-products (and-or) structure, allowing users to customize logic functions by programming the device for specific appli- cations. it provides up to 29 array inputs and 16 outputs. it incorporates amds unique input/output logic macro- cell which provides flexible input/output structure and polarity, flexible feedback selection, multiple output en- able choices, and a programmable clocking scheme. the macrocells can be individually programmed as combinatorial, registered, or latched with active-high or active-low polarity. the flexibility of the logic macro- cells permits the system designer to tailor the device to particular application requirements. increased logic power has been built into the PALCE29MA16 by providing a varied number of logic product terms per output. of the 16 outputs, 8 outputs have 4 product terms each, 4 outputs have 8 product terms each, and the other 4 outputs have 12 product terms each. this varied product-term distribution allows complex functions to be implemented in a single pal device. each output can be dynamically controlled by a common output enable pin or output enable product term. each output can also be permanently enabled or disabled. system operation has been enhanced by the addition of common asynchronous-preset and reset product terms and a power-up reset feature. the PALCE29MA16 also incorporates preload and obser- vability functions which permit full logic verification of the design. the PALCE29MA16 is offered in the space-saving 300-mil skinnydip package as well as the plastic leaded chip carrier package. connection diagrams top view i/of 7 i 3 skinnydip clk/ le i/of 3 v cc i/o 7 i/o 5 gnd i 2 i/of 2 i/o 1 i/of 1 i 0 i/of 6 i/o 6 i/ oe 1 3 5 7 9 11 12 10 2 4 8 6 24 22 20 18 16 14 13 15 23 21 17 19 i/of 0 i/o 0 i/o 3 i/o 2 i/o 4 i/of 5 i/of 4 plcc note: pin 1 is marked for orientation. i 1 i/of 0 i 0 clk/ le nc v cc i 3 i/of 7 1 32 4282726 i/o 7 i/o 6 nc i/o 5 i/o 4 i/of 5 6 7 8 9 10 11 19 20 i/o 0 i/o 2 i/o 3 i/of 2 24 23 22 21 i/of 6 5 i/of 1 25 i/of 3 i/ oe gnd i 1 i 2 i/of 4 12 13 17 15 16 14 18 i/o 1 nc nc pin designations clk/ le = clock or latch enable gnd = ground i = input i/o = input/output i/of = input/output with dual feedback v cc = supply voltage nc = no connection 08811g-2 08811g-3
amd 2-351 PALCE29MA16h-25 (com'l) ordering information commercial products technology ce = cmos electrically erasable family type pal = programmable array logic valid combinations amd programmable logic products for commercial applications are available with several ordering options. the order number (valid combination) is formed by a combination of these elements: valid combinations valid combinations lists configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. pal ce 29 ma 16 h -25 c /4 output type ma = advanced asynchronous macrocell number of flip-flops package type p = 24-pin plastic skinnydip (pd3024) j = 28-pin plastic leaded chip carrier (pl 028) temperature range c = commercial (0 c to +75 c) speed -25 = 25 ns power h = half power (100 ma) number of array inputs p programming revision /4 = first revision (requires current programming algorithm) optional processing blank = standard processing PALCE29MA16h-25 pc, jc /4
amd 2-352 PALCE29MA16h-25 functional description inputs the PALCE29MA16 has 29 inputs to drive each product term (up to 58 inputs with both true and complement versions available to the and array) as shown in the block diagram in figure 1. of these 29 inputs, 4 are dedicated inputs, 16 are from eight i/o logic macrocells with two feedbacks, 8 are from other i/o logic macro- cells with single feedback and one is the i/ oe input. initially the and-array gates are disconnected from all the inputs. this condition represents a logical true for the and array. by selectively programming the ee cells, the and array may be connected to either the true in- put or the complement input. when both the true and complement inputs are connected, a logical false re- sults at the output of the and gate. product terms the degree of programmability and complexity of a pal device is determined by the number of connections that form the programmable-and and or gates. each pro- grammable-and gate is called a product term. the PALCE29MA16 has 178 product terms; 112 of these product terms provide logic capability and others are ar- chitectural product terms. among the control product terms, one is for observability, and one is for preload. the output enable of each macrocell can be pro- grammed to be controlled by a common output enable pin or an individual product term. it may also be perma- nently disabled. in addition, independent product terms for each macrocell control preset, reset and clk/ le . each product term on the PALCE29MA16 consists of a 58-input and gate. the outputs of these and gates are connected to a fixed-or plane. product terms are allo- cated to or gates in a varied distribution across the device ranging from 4 to 12 wide, with an average of 7 logic product terms per output. an increased number of product terms per output allows more complex functions to be implemented in a single pal device. this flexibility aids in implementing functions such as counters, exclu- sive-or functions, or complex state machines, where different states require different numbers of product terms. individual asynchronous-preset and reset product terms are connected to all registered or latched i/os. when the asynchronous-preset product term is as- serted (high) the register or latch will immediately be loaded with a high, independent of the clock. when the asynchronous-reset product term is asserted (high) the register or latch will be immediately loaded with a low, independent of the clock. the actual output state will depend on the macrocell polarity selection. the latches must be in latched mode (not transparent mode) for the reset, preset, preload, and power-up reset modes to be meaningful. input/output logic macrocells the i/o logic macrocell allows the user the flexibility of defining the architecture of each input or output on an in- dividual basis. it also provides the capability of using the associated pin either as an input or an output. the PALCE29MA16 has 16 macrocells, one for each i/o pin. each i/o macrocell can be programmed for combinatorial, registered or latched operation (see fig- ure 2). combinatorial output is desired when the pal device is used to replace combinatorial glue logic. reg- isters and latches are used in synchronous logic applications. registers and latches with product term controlled clocks can also be used in asychronous application. v 1 0 preset reset s2 s3 1 1 1 0 0 1 0 0 s4 s5 common i/ oe (pin) individual oe individual asynchronous preset p0 p7 or p11 common clk/ le (pin) individual clk/ le individual asynchronous reset to and array i/o s6 s7 v cc s0 s1 d q 0 1 1 1 1 0 0 0 1 1 0 1 1 0 0 0 q clk/ le 1 0 s8 x r x 08811g-4 figure 2a. PALCE29MA16 macrocell (single feedback)
amd 2-353 PALCE29MA16h-25 the output polarity for each macrocell in each of the three modes of operation is user-selectable, allowing complete flexibility of the macrocell configuration. eight of the macrocells (i/of 0 Ci/of 7 ) have two inde- pendent feedback paths to the and array (see figure 2b). the first is a dedicated i/o pin feedback to the and array for combinatorial input. the second path consists of a direct register/latch feedback to the array. if the pin is used as a dedicated input using the first feedback path, the register/latch feedback path is still available to the and array. this path provides the capability of using the register/latch as a buried state register/latch. the other eight macrocells have a single feedback path to the and array. this feedback is user-selectable as either an i/o pin or a register/latch feedback (see figure 2a). each macrocell can provide true input/output capability. the user can select each macrocell register/latch to be driven by either the signal generated by the and-or ar- ray or the corresponding i/o pin. when the i/o pin is se- lected as the input, the feedback path provides the register/latch input to the array. when used as an input, each macrocell is also user-programmable for regis- tered, latched, or combinatorial input. the PALCE29MA16 has a dedicated clk/ le pin and one individual clk/ le product term or macrocell. all macrocells have a programmable switch to choose be- tween the clk/ le pin and the clk/ le product term as the clock or latch enable signal. these signals are clock signals for macrocells configured as registers and latch enable signals for macrocells configured as latches. the polarity of these clk/ le signals is also individually programmable. thus different registers or latches can be driven by different clocks and clock phases. the output-enable mode of each of the macrocells can be selected by the user. the i/o pin can be configured as an output pin (permanently enabled) or as an input pin (permanently disabled). it can also be configured as a dynamic i/o controlled by the output enable pin or by a product term. i/o logic macrocell configuration amds unique i/o macrocell offers major benefits through its versatile, programmable input/output cell structure, multiple clock choices, flexible output enable and feedback selection. eight i/o macrocells with single feedback contain 9 ee cells, while the other eight ma- crocells contain 8 ee cells for programming the input/ output functions (see table 1). ee cell s 1 controls whether the macrocell will be combi- natorial or registered/latched. s 0 controls the output po- larity (active-high or active-low). s 2 determines whether the storage element is a register or a latch. s 3 allows the use of the macrocell as an input register/latch or as an output register/latch. it selects the direction of the data path through the register/latch. if connected to the usual and-or array output, the register/latch is an output connected to the i/o pin. if connected to the i/o pin, the register/latch becomes an input register/latch to the and array using the feedback data path. programmable ee cells s 4 and s 5 allow the user to se- lect one of the four clk/ le signals for each macrocell. s 6 and s 7 are used to control output enable as pin con- trolled, product-term controlled, permanently enabled or permanently disabled. s 8 controls a feedback multi- plexer for the macrocells with a single feedback path only. using the programmable ee cells s 0 Cs 8 various input and output configurations can be selected. some of the possible configuration options are shown in figure 3. in the erased state (charged, disconnected), an archi- tectural cell is said to have a value of 1; in the pro- grammed state (discharged, connected to gnd), an architectural cell is said to have a value of 0. v 1 0 preset reset s2 s3 1 1 1 0 0 1 0 0 s4 s5 common i/ oe (pin) individual oe individual asynchronous preset p0 p3 common clk/ le (pin) individual clk/ le individual asynchronous reset to and array i/of s6 s7 v cc s0 s1 d q 0 1 1 1 1 0 0 0 1 1 0 1 1 0 0 0 q clk/ le x rf x to and array figure 2b. PALCE29MA16 macrocell (dual feedback) 08811g-5
amd 2-354 PALCE29MA16h-25 table 1a. PALCE29MA16 i/o logic macrocell architecture selections s 2 storage element 1 register 0 latch s 3 i/o cell 1 output cell 0 input cell s 0 output polarity 1 active low 0 active high s 1 output type 1 combinatorial 0 register/latch s 8 feedback* 1 register/latch 0 i/o *applies to macrocells with single feedback only. table 1b. PALCE29MA16 i/o logic macrocell clock polarity and output enable selections s 4 s 5 clock edge/latch enable level 1 1 clk/ le pin positive-going edge, active-low le* 1 0 clk/ le pin negative-going edge, active-high le* 0 1 clk/ le pt positive-going edge, active-low le* 0 0 clk/ le pt negative-going edge, active-high le* s 6 s 7 output buffer control 1 1 pin-controlled three-state enable 1 0 pt-controlled three-state enable 0 1 permanently enabled (output only) 0 0 permanently disabled (input only) notes: 1 = erased state (charged or disconnected). 0 = programmed state (discharged or connected). *active-low le means that data is stored when the le pin is high, and the latch is transparent when the le pin is low. active-high le means the opposite.
amd 2-355 PALCE29MA16h-25 some possible configurations of the input/output logic macrocell (for other useful configurations, please refer to the macrocell diagrams in figure 2. all macrocell architecture cells are independently programmable). v dq q s = 1 s = 0 s = 1 s = 1 0 1 3 2 output registered/active low v dq q s = 1 s = 1 s = 1 0 1 3 output combinatorial/active low v dq q s = 0 s = 0 s = 1 s = 1 0 1 3 2 output registered/active high v dq q s = 0 s = 1 s = 1 0 1 3 output combinatorial/active high 08811g-6 08811g-7 08811g-8 08811g-9 figure 3a. dual feedback macrocells dq s = 1 s = 0 s = 1 s = 0 s = 1 0 1 3 8 2 q v output registered/active low, i/o feedback s = 1 s = 1 s = 1 s = 0 0 1 3 8 output combinatorial/active low, i/o feedback dq le s = 0 s = 0 s = 1 s = 0 s = 0 0 1 3 8 2 q output latched/active high, i/o feedback s = 0 s = 1 s = 1 s = 0 0 1 3 8 output combinatorial/active high, i/o feedback 08811g-10 08811g-11 08811g-12 08811g-13 figure 3b. single feedback macrocells
amd 2-356 PALCE29MA16h-25 some possible configurations of the input/output logic macrocell v dq q s = 1 s = 0 s = 1 s = 1 s = 1 0 1 3 8 2 output registered/active low, register feedback dq q s = 1 s = 1 s = 1 s = 1 s = 1 0 1 3 8 2 v output combinatorial/active low, latched feedback dq q s = 1 s = 0 s = 1 s = 1 s = 0 0 1 3 8 2 le output latched/active low, latched feedback dq q s = 1 s = 1 s = 1 s = 1 s = 0 0 1 3 8 2 le output combinatorial/active low, latched feedback 08811g-14 08811g-15 08811g-16 08811g-17 figure 3b. single feedback macrocells (continued) d q s = 0 s = 1 (for single feedback only) s = 1 register = 0 latch 3 8 2 v programmable-and array programmable-and array 08811g-18 figure 3c. all macrocells
amd 2-357 PALCE29MA16h-25 power-up reset all flip-flops power up to a logic low for predictable sys- tem initialization. the outputs of the PALCE29MA16 depend on whether they are selected as registered or combinatorial. if registered is selected, the output will be low if programmed as active low and high if pro- grammed as active high. if combinatorial is selected, the output will be a function of the logic. preload to simplify testing, the PALCE29MA16 is designed with preload circuitry that provides an easy method for test- ing logical functionality. both product-term-controlled and supervoltage-enabled preload modes are available. the ttl-level preload product term can be useful during debugging, where supervoltages may not be available. preload allows any arbitrary state value to be loaded into the registers/latches of the device. a typical func- tional-test sequence would be to verify all possible state transitions for the device being tested. this requires the ability to set the state registers into an arbitrary present state value and to set the devices inputs into an arbi- trary present input value. once this is done, the state machine is clocked into a new state, or next state, which can be checked to validate the transition from the present state. in this way any transition can be checked. since preload can provide the capability to go directly to any desired arbitrary state, test sequences may be greatly shortened. also, all possible states can be tested, thus greatly reducing test time and development costs and guaranteeing proper in-system operation. observability the output register/latch observability product term, when asserted, suppresses the combinatorial output data from appearing on the i/o pin and allows the obser- vation of the contents of the register/latch on the output pin for each of the logic macrocells. this unique feature allows for easy debugging and tracing of the buried state machines. in addition, a capability of supervoltage ob- servability is also provided. security cell a security cell is provided on each device to prevent un- authorized copying of the users proprietary logic de- sign. once programmed, the security cell disables the programming, verification, preload, and the obser- vability modes. the only way to erase the protection cell is by erasing the entire array and architecture cells, in which case no proprietary design can be copied. (this cell should be programmed only after the rest of the de- vice has been completely programmed and verified.) programming and erasing the PALCE29MA16 can be programmed on standard logic programmers. it may also be erased to reset a pre- viously configured device back to its virgin state. erasure is automatically performed by the programming hardware. no special erasure operation is required. quality and testability the PALCE29MA16 offers a very high level of built-in quality. the erasability of the device provides a direct means of verifying performance of all the ac and dc pa- rameters. in addition, this verifies complete pro- grammability and functionality of the device to yield the highest programming yield and post-programming func- tional yield in the industry. technology the high-speed PALCE29MA16 is fabricated with amds advanced electrically-erasable (ee) cmos process. the array connections are formed with proven ee cells. inputs and outputs are designed to be compat- ible with ttl devices. this technology provides strong input-clamp diodes, output slew-rate control, and a grounded substrate for clean switching.
amd 2-358 PALCE29MA16h-25 logic diagram skinny dip (plcc) pinouts input/ output macro input/ output macro input/ output macro input/ output macro input/ output macro input/ output macro input/ output macro input/ output macro observe product term (3) 2 i (4) 3 i/of (5) 4 i/of (6) 5 i/o (7) 6 i/o 0 48 12 16 20 24 28 32 36 40 44 48 52 56 19 (23) i/o 20 (24) i/o 22 (26) i/of 23 (27) i 21 (25) i/of continued on next page clk/ le (2) 1 0 0 1 0 1 6 6 7 3 7 08811g-19
amd 2-359 PALCE29MA16h-25 logic diagram skinny dip (plcc) pinouts 08811g-19 (concluded) input/ output macro input/ output macro 14 (17) i 13 (16) i 15 (18) i/of 16 (19) i/of 17 (20) i/o 18 (21) i/o (9) 7 i/o (10) 8 i/o (11) 9 i/of (12) 10 i/of (13) 11 i/ oe preload product term 048 12 16 20 24 28 32 36 40 44 48 52 56 continued from previous page 048 12 16 20 24 28 32 36 40 44 48 52 56 2 3 2 3 2 1 4 5 4 5 input/ output macro input/ output macro input/ output macro input/ output macro input/ output macro input/ output macro
amd 2-360 PALCE29MA16h-25 (com'l) absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to +7.0 v . . . . . . . . . . . . . dc input voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . static discharge voltage 2001 v . . . . . . . . . . . . . . . . . latchup current (t a = 0 c to +75 c) 100 ma . . . . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliabil- ity. programming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air 0 c to +75 c . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise specified notes: 1. these are absolute values with respect to device ground all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. parameter symbol parameter description test conditions min max unit v oh output high voltage i oh = C2 ma v in = v ih or v il 2.4 v v cc = min v ol output low voltage i ol = 8 ma v in = v ih or v il 0.5 i ol = 4 ma v cc = min 0.33 v i ol = 20 m a 0.1 v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 1) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 1) i ih input high leakage current v in = 5.5 v, v cc = max (note 2) 10 m a i il input low leakage current v in = 0 v, v cc = max (note 2) C10 m a i ozh off-state output leakage v out = 5.5 v, v cc = max 10 m a current high v in = v ih or v il (note 2) i ozl off-state output leakage v out = 5.5 v, v cc = max C10 m a current low v in = v ih or v il (note 2) i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C130 ma i cc supply current v in = 0 v, outputs open (i out = 0 ma) 100 ma v cc = max
amd 2-361 PALCE29MA16h-25 (com'l) capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 0 v v cc = 5.0 v, t a = 25 c, 5 pf c out output capacitance v out = 0 v f = 1 mhz 8 pf note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. switching characteristics registered operation parameter symbol parameter description min max unit combinatorial output t pd input or i/o pin to combinatorial output 25 ns output register C pin clock t sor input or i/o pin to output register setup 15 ns t cor output register clock to output 15 ns t hor data hold time for output register 0 ns output register C product term clock t sorp i/o pin or input to output register setup 4 ns t corp output register clock to output 29 ns t horp data hold time for output register 10 ns input register C pin clock t sir i/o pin to input register setup 2 ns t cir register feedback clock to combinatorial output 28 ns t hir data hold time for input register 6 ns clock and frequency t cis register feedback (pin driven clock) to output 20 ns register/latch (pin driven) setup t cispp register feedback (pt driven clock) to output 25 ns register/latch (pt driven) setup f max maximum frequency (pin driven) 1/(t sor + t cor ) 33.3 mhz f maxi maximum internal frequency (pin driven) 1/t cis 50 mhz f maxp maximum frequency (pt driven) 1/(t sorp + t corp ) 30 mhz f maxipp maximum internal frequency (pt driven) 1/t cispp 40 mhz t cwh pin clock width high 8 ns t cwl pin clock width low 8 ns t cwhp pt clock width high 12 ns t cwlp pt clock width low 12 ns
amd 2-362 PALCE29MA16h-25 v v output register t cor t cir clk input register t sir t sor cis t input/output register specs (pin clk reference) v i/o i/o t pd i/o i/o t pd and-or array cis t 08811g-20 v v output register t corp clk input input register t sorp cispp t input/output register specs (pt clk reference) v i/o i/o t pd i/o i/o t pd and-or array cispp t 08811g-21
amd 2-363 PALCE29MA16h-25 switching waveforms input register combinatorial output clock v t v t v t v t registered input t sir t hir cir t output register (pt clock) combinatorial input combinatorial input as clock v t v t v t v t registered output t sorp t horp t corp output register (pin clock) combinatorial input clock v t v t v t v t registered output t sor t hor t cor combinatorial output combinatorial input v t v t combinatorial output t pd combinatorial output output register (pt clock) input register output register (pin clock) 08811g-22 08811g-23 08811g-24 08811g-25
amd 2-364 PALCE29MA16h-25 switching waveforms pt clock width combinatorial input as clock v t v t v t cwlp t cwhp t cispp t pin clock width clock v t v t v t t cwh t cis t cwl pin clock width pt clock width 08811g-26 08811g-27
amd 2-365 PALCE29MA16h-25 (com'l) switching characteristics latched operation parameter symbol parameter description min max unit combinatorial output t pd input or i/o pin to combinatorial output 25 ns t ptd input or i/o pin to output via transparent latch 28 ns output latch C pin le t sol input or i/o pin to output register setup 15 ns t gol latch enable to transparent mode output 15 ns t hol data hold time for output latch 0 ns t stl input or i/o pin to output latch setup via 18 ns transparent input latch output latch C product term le t solp input or i/o pin to output latch setup 4 ns t golp latch enable to transparent mode output 29 ns t holp data hold time for output latch 10 ns t stlp input or i/o pin to output latch setup via 10 ns transparent input latch input latch C pin le t sil i/o pin to input latch setup 2 ns t gil latch feedback, latch enable transparent mode to 28 ns combinatorial output t hil data hold time for input latch 6 ns latch enable t gis latch feedback (pin driven) to output register/latch 20 ns (pin driven) setup t gispp latch feedback (pt driven) to output register/latch 25 ns (pt driven) setup t gwh pin enable width high 8 ns t gwl pin enable width low 8 ns t gwhp pt enable width high 12 ns t gwlp pt enable width low 12 ns
amd 2-366 PALCE29MA16h-25 output latch t golp gispp t ptd t i/o i/o t ptd t pd le input input latch t stlp t ptd i/o i/o t solp t ptd t pd and-or array gispp t input/output latch specs (pt le reference) output latch gis t gol t ptd t i/o i/o t gil t ptd t pd le input latch t stl t sil t ptd i/o i/o t sol t ptd t pd and-or array gis t input/output latch specs (pin le reference) 08811g-28 08811g-29
amd 2-367 PALCE29MA16h-25 switching waveforms pt le width combinatorial input as le latched transparent v t v t v t gwlp t gwhp t input latch (pin le ) le latched input combinatorial output transparent v t t sil t hil t gil t ptd v t v t v t v t v t output latch (pt le ) latched output latched input combinatorial input transparent v t v t v t v t v t v t t stlp t solp t holp t golp t ptd combinatorial input as le transparent latched pin le width v t v t v t gwh t t gwl le output latch (pin le ) le latched output latched input combinatorial input transparent v t v t v t v t v t v t v t t sol t hol t gol t ptd t ptd t stl note 1 combinatorial output latched output latched input combinatorial input latch (transparent mode) t v t v t v t v t ptd t pd t ptd note: 1. if the combinatorial input changes while le is in the latched mode and le goes into the transparent mode after t ptd ns has elasped, the corresponding latched output will change t gol ns after le goes into the transparent mode. if the com- binatorial input changes while le is in the latched mode and le goes into the transparent mode before t ptd ns has elapsed, the corresponding latched output will change at the later of the following C t ptd ns after the combinatorial input changes or t gol ns after le goes into the latched mode. input and output latch relationship v t latched transparent v t transparent latched input latch output latch t gis le le 08811g-30 08811g-31 08811g-32 08811g-33 08811g-34 08811g-35 08811g-36
amd 2-368 PALCE29MA16h-25 (com'l) switching characteristics reset/preset, enable note: 1. output disable times do not include test load rc time constants. parameter symbol parameter description min max unit t apo input or i/o pin to output register/latch 30 ns reset/preset t aw asynchronous reset/preset pulse width 15 ns t aro asynchronous reset/preset to output 15 ns register/latch recovery t ari asynchronous reset/preset to input 12 ns register/latch recovery t arpo asynchronous reset/preset to output 4 ns register/latch recovery pt clock/le t arpi asynchronous reset/preset to input 6 ns register/latch recovery pt clock/le output enable operation t pzx i/ oe pin to output enable 20 ns t pxz i/ oe pin to output disable (note 1) 20 ns t ea input or i/o to output enable via pt 25 ns t er input or i/o to output disable via pt (note 1) 25 ns switching waveforms input register/latch reset/preset combinatorial asynchronous reset/preset v t v t clock t aw t ari v t pin 11 combinatorial/ registered/ latched output pin 11 to output disable/enable t pxz t pzx v ol + 0.5 v v oh - 0.5 v v t output register/latch reset/preset combinatorial asynchronous reset/preset registered/ latched output v t v t v t clock t aro t aw t apo 08811g-37 08811g-39 08811g-38 combinatorial/ registered/ latched output input to output disable/enable t er t ea v ol + 0.5 v v oh - 0.5 v v t v t combinatorial input 08811g-40
amd 2-369 PALCE29MA16h-25 key to switching waveforms ks000010-pal must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs switching test circuit specification switch s 1 c l r 1 r 2 measured output value t pd , t co , t gol closed 1.5 v t ea , t pzx z ? h: open 1.5 v z ? l: closed t er , t pxz h ? z: open 5 pf h ? z: v oh C0.5 v l ? z: closed l ? z: v ol +0.5 v 5 v output s 1 r 1 r 2 c l 390 w 35 pf 470 w 08811g-41
amd 2-370 PALCE29MA16h-25 preload the PALCE29MA16 has the capability for product-term preload. when the global-preload product term is true, the PALCE29MA16 will enter the preload mode. this feature aids functional testing by allowing direct setting of register states. the procedure for preload is as follows: n set the selected input pins to the user selected preload condition. n apply the desired register value to the i/o pins. this sets q of the register. the value seen on the i/o pin, after preload, will depend on whether the macrocell is active high or active low. n pulse the clock pin (pin 1). n remove the inputs to the i/o pins. n remove the preload condition. n verify v ol /v oh for all output pins as per pro- grammed pattern. because the preload command is a product term, any input to the array can be used to set preload (including i/o pins and registers). preload itself will change the val- ues of the i/o pins and registers. this will have unpre- dictable results. therefore, only dedicated input pins should be used for the preload command. parameter symbol parameter description min rec. max unit t d delay time 0.5 1.0 5.0 m s t w pulse width 250 500 700 ns t i/o valid output 100 500 ns t d v ih inputs i/o pins clk pin 1 (2) t d t d t w v il v oh /v ih v ol /v il v il v ih t io preload mode data to be preloaded 08811g-42 preload waveform
amd 2-371 PALCE29MA16h-25 observability the PALCE29MA16 has the capability for product-term observability. when the global-observe product term is true, the PALCE29MA16 will enter the observe mode. this feature aids functional testing by allowing direct ob- servation of register states. when the PALCE29MA16 is in the observe mode, the output buffer is enabled and the i/o pin value will be q of the corresponding register. this overrides any oe inputs. the procedure for observe is: n remove the inputs to all the i/o pins. n set the inputs to the, user selected, observe configuration. n the register values will be sent to the correspond- ing i/o pins. n remove the observe configuration from the se- lected i/o pins. because the observe command is a product term, any input to the array can be used to set observe (including i/o pins and registers). if i/o pins are used, the observe mode could cause a value change, which would cause the device to oscillate in and out of the observe mode. therefore, only dedicated input pins should be used for the observe command. parameter symbol parameter description min rec. max unit t d delay time 0.5 1.0 5.0 m s t i/o valid output 100 500 ns t d v ih input pins i/o pins clk pin 1 (2) v il v il t io v ih v ol v oh observe mode 08811g-43 observability waveform
amd 2-372 PALCE29MA16h-25 power-up reset the registered devices in the amd pal family have been designed with the capability to reset during system power-up. following power-up, all registers will be reset to low. the output state will depend on the polarity of the output buffer. this feature provides extra flexibility to the designer and is especially valuable in simplify- ing state machine initialization. a timing diagram and parameter table are shown below. due to the asynchronous operation of the power-up reset, and the wide range of ways v cc can rise to its steady state, two conditions are required to ensure a valid power-up re- set. these conditions are: n the v cc rise must be monotonic. n following reset, the clock input must not be driven from low to high until all applicable input and feedback setup times are met. parameter symbol parameter description min max unit t pr power-up reset time 10 m s t s input or feedback setup time t w clock width t r v cc rise time 500 m s see switching characteristics t pr t w t s 4 v v cc power registered active low output clock t r 08811g-44 power-up reset waveform
amd 2-373 PALCE29MA16h-25 typical thermal characteristics measured at 25 c ambient. these parameters are not tested. parameter symbol parameter description skinnydip plcc unit q jc thermal impedance, junction to case 17 11 c/w q ja thermal impedance, junction to ambient 63 51 c/w q jma thermal impedance, junction to ambient with air flow 200 lfpm air 60 43 c/w 400 lfpm air 52 38 c/w 600 lfpm air 43 34 c/w 800 lfpm air 39 30 c/w typ plastic q jc considerations the data listed for plastic q jc are for reference only and are not recommended for use in calculating junction temperatures. the heat-flow paths in plastic-encapsulated devices are complex, making the q jc measurement relative to a specific location on the package surface. tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. furthermore, q jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. therefore, the measurements can only be used in a similar environment.

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